Posted Apr 7, 2026
As an experienced VLSI Verification Engineer specializing in PCIe protocol, your role involves ensuring the correctness and compliance of high-speed interfaces with industry standards. Your responsibilities will include:
Developing and executing verification plans for PCIe-based IPs and subsystems. - Creating testbenches using SystemVerilog/UVM methodology. - Performing simulation, debugging, and coverage analysis for design quality assurance. - Collaborating closely with design teams to address specifications and resolve issues. - Implementing assertions, scoreboards, and monitors for protocol compliance. - Analyzing and reporting functional coverage metrics to enhance test quality. - Participating in code reviews and contributing to verification methodology enhancements. Your required skills for this role include:
Strong knowledge of PCIe protocol (Gen3/Gen4/Gen5 preferred). - Hands-on experience with SystemVerilog and UVM. - Proficiency in simulation tools such as Synopsys VCS, Cadence Xcelium, and Mentor Questa. - Experience in debugging waveform and log files. - Familiarity with coverage-driven verification and assertion-based verification. - Good understanding of digital design concepts and SoC/IP verification flows. Preferred skills that would be beneficial for this position are:
Exposure to C/C++ or Python scripting for automation. - Knowledge of other high-speed protocols like Ethernet, USB, and DDR. - Experience with formal verification and emulation platforms. - Familiarity with version control systems like Git and Perforce. Education requirement for this role is a degree in Electronics, Electrical, or Computer Engineering (B.E./B.Tech/M.E./M.Tech). In addition to technical skills, soft skills such as strong analytical abilities, excellent communication, teamwork skills, and the capability to work in a fast-paced environment and meet deadlines are essential for success in this role. As an experienced VLSI Verification Engineer specializing in PCIe protocol, your role involves ensuring the correctness and compliance of high-speed interfaces with industry standards. Your responsibilities will include:
Developing and executing verification plans for PCIe-based IPs and subsystems. - Creating testbenches using SystemVerilog/UVM methodology. - Performing simulation, debugging, and coverage analysis for design quality assurance. - Collaborating closely with design teams to address specifications and resolve issues. - Implementing assertions, scoreboards, and monitors for protocol compliance. - Analyzing and reporting functional coverage metrics to enhance test quality. - Participating in code reviews and contributing to verification methodology enhancements. Your required skills for this role include:
Strong knowledge of PCIe protocol (Gen3/Gen4/Gen5 preferred). - Hands-on experience with SystemVerilog and UVM. - Proficiency in simulation tools such as Synopsys VCS, Cadence Xcelium, and Mentor Questa. - Experience in debugging waveform and log files. - Familiarity with coverage-driven verification and assertion-based verification. - Good understanding of digital design concepts and SoC/IP verification flows. Preferred skills that would be beneficial for this position are:
Exposure to C/C++ or Python scripting for automation. - Knowledge of other high-speed protocols like Ethernet, USB, and DDR. - Experience with formal verification and emulation platforms. - Familiarity with version control systems like Git and Perforce. Education requirement for this role is a degree in Electronics, Electrical, or Computer Engineering (B.E./B.Tech/M.E./M.Tech). In addition to technical skills, soft skills such as strong analytical abilities, excellent communication, teamwork skills, and the capability to work in a fast-paced environment and meet deadlines are essential for success in this role.
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