Senior Verification Engineer

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive's phenomenal success and to see why we have won the GSA's prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: The Role SiFive is looking for a Senior Design Verification Engineer to drive verification of cache and memory-subsystem functionality, with an emphasis on cache coherency, ordering, correctness, and subsystem integration. This is a Senior Engineer individual-contributor role within the horizontal cache verification area. We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the team. Responsibilities Understand the cache and memory-subsystem architecture and create effective verification strategies and test plans for the assigned area. Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for cache coherency, ordering, flow control, and error scenarios. Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, backpressure, and integration behavior. Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content. Collaborate closely with architecture, design, and verification teams to clarify requirements, review specifications, and improve verification quality early in the development cycle. Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality. Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 3+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in CPU, memory-system, or cache verification. Strong hands-on experience with SystemVerilog and UVM-based verification. Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts. Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues. Strong problem-solving skills and the ability to work effectively across design and verification teams. Preferred Qualifications Direct experience verifying cache or memory-subsystem functionality, including coherency behavior in multicore systems. Experience with subsystem integration and protocol interactions across multiple interfaces or bridge paths. Familiarity with scripting and automation using Python or similar languages. Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug is a plus. What Success Looks Like Verification plans are complete and aligned with the highest architectural risks. Critical bugs are found early, debugged efficiently, and closed with durable fixes. Coverage and verification quality improve meaningfully under your ownership. The cache verification effort becomes more scalable, reusable, and predictable because of your contributions. Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: Taiwan Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. Championed by leaders who chose to make a real difference, SiFive led the RISC-V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we've made history, you have the opportunity to write the future. If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.