Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead.

We are seeking a high-caliber Staff or Senior Staff Engineer to lead SOC Timing Convergence. This is a critical leadership role for a driven, "go-getter" engineer who excels at navigating the complexities of modern, large-scale SOC designs. You will be the bridge between Architecture, RTL, DFT, and Physical Design to ensure a predictable, high-performance path to tape-out. ---

The Role

As a lead for SOC Timing or SubChip Timing, you will own the strategy for convergence. You will identify bottlenecks early in the design cycle ("left-shifting") and drive cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities

• Timing Convergence Leadership: Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.). -  Partner with  to validate timing feasibility,  to optimize logic structures, and  to streamline test-mode timing. -  Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution. -  Perform complex timing tasks including  analysis,  (Network-on-Chip) timing, and constraint validation (SDC). -  Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility. -  Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations. ---