Sr. Staff RTL Eng

Independent, self-motivated, and capable of executing in dynamic environments

Innovative problem solver with a focus on creating better solutions

Strong communication skills and ability to work effectively in a team environment

Proficiency in technical documentation Join Team Lattice Semiconductor and be part of the sensAI team, driving innovation in enabling edgeAI with programmable low power devices. Your contributions will help add intelligence to sensors used in Automotive, industrial, and consumer products, creating a smarter and better-connected world. Together, we enable whats next. As a Senior Staff Design Engineer at Lattice Semiconductor, you will be responsible for designing and developing RTL for a Machine Learning engine. Your primary focus will be implementing ML operators efficiently on low power FPGA platforms. Your expertise in optimizing data paths for high throughput and low latency will be crucial for the success of this role. Additionally, a good understanding of neural network accelerators and DSP processors is essential. Key Responsibilities:

Design and develop RTL using Verilog and System Verilog-HDL

Conduct functional simulation using tools like Xcelium-Cadence and VCS-Synopsys

Architect and design RTL for Machine Learning compute engines on low-power FPGA platforms

Collaborate with algorithm and architecture teams to translate ML models into efficient hardware micro-architectures

Implement image processing and DSP algorithms

Utilize deep understanding of machine learning and data models to optimize hardware mapping

Work on FPGA/ASIC synthesis flow and timing closure

Apply knowledge of computer architecture and memory management

Familiarity with C and/or SystemC is a plus