Staff Engineer for RAS

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive's phenomenal success and to see why we have won the GSA's prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages. Job Description: Key Responsibilities: Lead the verification and optimization of our diverse RISC-V RAS Profiles, including Functional Safety (FuSa) profiles. Drive and achieve quality closure targets at both the CPU and block levels. Collaborate closely with microarchitecture and RTL design teams to optimize complex RAS flows. Provide technical leadership and mentorship to junior team members to foster team growth and enrichment. Actively participate in the test planning and execution phases for new architecture and design features. Required Qualifications: 10+ years of overall industry experience, with a demonstrated ability to lead and execute complex verification efforts. Expertise in verification methodologies for error injection, particularly within SRAM and other design modules. Must possess hands-on, proficient debugging skills, specifically utilizing CPU Assembly (ASM) execution. A strong understanding of CPU microarchitecture, along with key concepts in RAS (Reliability, Availability, and Serviceability) and ECC (Error-Correcting Code). Demonstrated ability to work effectively as part of a team, believing in a collaborative engineering approach. Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. Championed by leaders who chose to make a real difference, SiFive led the RISC-V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we've made history, you have the opportunity to write the future. If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.